The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for manufacturing a smaller contact structure for a cell of a MOS transistor device. Merely by way of example, the invention has been applied to a standard MOS transistor device for integrated circuits. But it would be recognized that the invention can be applied to a variety of applications such as memories, application specific integrated circuits, microprocessors, any combination of these, and the like.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the ability to reduce a cell size of a semiconductor device in a cost efficient and efficient way.
Various techniques have been used to reduce the cell size of semiconductor devices. An example of such techniques includes the use of sidewall spacers on edges of metal oxide silicon (MOS) gate structures. Such sidewall spacers are used to form a self-aligned contact region, which is smaller in size and more efficient to manufacture. Other techniques use increasing smaller gate structure, shallower implanting techniques, among others. Unfortunately, many limitations exist with the convention semiconductor devices. Often times, it is difficult to reduce a cell size less than 70 nanometers of a critical dimension of the gate structure. The reduced cell size is based upon practical limits of processes and equipment used for the manufacture of semiconductor devices. These and other limitations are described throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.